Principal Physical Design Verification / ESD Engineer
Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing. By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.
Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply!
About the role:
As a member of the PDV Team, you'll own chip-level physical design verification, physical verification flow automation, physical design reviews and ESD coverage.
What you’ll achieve:
- Partition and chip-level level ownership of physical design verification (PDV), and physical design reviews
- Execute and debug final verification flows in preparation for gds tape out delivery on FinFet designs (DRC, LVS,DFM, Antenna, Density Fill Routines, XOR, etc.)
- ESD Verification and Sign-off at partition and chip level
- Design enhancements and DFM techniques
- Package level physical verification
- LVS / DRC check coding
- Support all PDV sign-off scripts at partition and at chip-level
- Work with multiple sites in a team environment, particularly with offices in the US, India, and Vietnam
About you:
- M.Tech in Electronics Engineering or Computer Engineering with 6+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 8+ years of semiconductor experience
- Background with FinFets and multi exposure metallization is required
- Familiarity with Cadence and Siemens tools is required
- Shell, Skill, Calibre and other programming knowledge
- Familiarity with Physical Verification flow automation
- Familiarity with ESD coverage techniques and verifications flows (Calibre PERC, Ansys Pathfinder)
- Familiarity with DFM techniques for yield enhancements
- Familiar in identifying and addressing issues often found at the chip level, some of which include:
- Density
- Latch up triggered failures
- Abutment conflicts
- Data integrity
- Short isolation and open/swapped nets
What we’ll offer:
- Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work.
- Generous paid time off policy so that you can embrace a healthy work-life balance
- Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.