Technical Intern, Design Implementation Engineer
Description
Invent the future with us.
Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.
By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.
Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply!
About the role:
- We are looking for a Technical Intern for Design Implementation team to help us grow our team. You will be responsible for ASIC Design implementation on our cutting edge ARMv9 based server on chip solutions that will be the backbone of future data centers and also the AI Inference Server. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology nodes available in the industry.
- Being a Technical Intern, Design Implementation Engineer at Ampere® is interesting, challenging, and will expand your professional breadth. You will learn how the next generation Microprocessor for Cloud Computing developed in Ampere®, powered by Arm64-core and our in-house tooling, to achieve highest performance versus power consumption. And you will learn how a product is developed from R&D to delivery. The experience at Ampere® that you will possess will be valuable for your career path.
What you’ll achieve:
- Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off.
- Develop mid-end to back end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc.
- Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners.
- Perform timing closure across all corners to ensure successful tapeout following our aggressive deadlines.
- Generate and implement functional ECO.
- Run Logic Equivalent Check (LEC) from RTL to prelayout/ postlayout netlist
About you:
- Have some basic working knowledge of Semiconductor devices, VLSI designs, ASIC design flow, etc.
- Familiar with UNIX, C, Verilog and Office applications
- Good understanding on SoC, Pcie design is an advantage
- Good debugging, problem solving and presentation skills
- Good communication skills in English and Vietnamese
Education:
- Candidate must be pursuing a Bachelor’s Degree in Computer Engineering/ Electrical and Electronic Engineering as the final year Students with a strong academic record or equivalent
What we’ll offer:
At Ampere we believe in taking care of our interns and providing a competitive monthly stipend and allowance.
Benefits highlights include:
- Mentorship and on-the-job training from industry experts
- Daily catered lunch, a variety of snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.
- Intern events, cultural and engagement activities with the team and the company
At Ampere, we foster an inclusive culture that empowers our interns to do more and grow more. We are excited to share more about our internship opportunities with you through the interview process.