DFT Engineer ( Scan / ATPG)
Description
Invent the future with us.
Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient AI compute.
As a pioneer in the new frontier of energy efficient high-performance computing, Ampere is part of the Softbank Group of companies driving sustainable computing for AI, Cloud, and edge applications.
Join us at Ampere and work alongside a passionate and growing team - we’d love to have you apply!
About the role:
Our DFT Engineer will work with multi-functional global teams to design, implement and verify SCAN, ATPG (Stuck-AT/AT-Speed), MBIST, IO BIST and JTAG/IJTAG DFT features on our next generation highly complex server class processor products.
In this role, you will be at the forefront of AI innovation, building AmpereOne Aurora, our groundbreaking AI compute solution. Aurora combines high-performance general-purpose CPUs with integrated AI capabilities, offering a compelling combination of efficiency and market reach. This revolutionary product is poised to deliver superior performance while consuming significantly less power.
What you’ll achieve:
As a member of the DFT Team, you will architect and design a significant portion of the DFT feature partnering with design, verification, test, and silicon engineering peers. In addition, you will create solutions to meet challenging frequency, power, coverage, and test time reduction goals.
About you:
- M.Tech in Electronics Engineering or Computer Engineering with 3+ years of semiconductor experience or B.Tech in Electronics Engineering or Computer Engineering with 5+ years of semiconductor experience
- Experience in Scan insertion with compression for Stuck-At and At-Speed test.
- Experience in Scan ATPG (Stuck-At and At-Speed), coverage analysis, simulation and debug
- Experience in MBIST insertion, simulation and debug on RTL and gates netlist
- Experience in Boundary Scan insertion, simulation and verification.
- Hands on knowledge in state-of-the-art EDA tools for DFT, design and verification.(Mentor, Cadence, Synopsys)
- Good written and verbal communication skills in English
- STA DFT Test mode timing constraint development and analysis is a plus
- Knowledge of Verilog HDL and experience with simulators and waveform debugging tools
- Experience with ATE silicon debug and utilize scripting with perl/Tcl for efficient handling of ATE data a plus.
What we’ll offer:
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, cash long-term incentive, and comprehensive benefits.
Benefits highlights include:
- Premium medical, dental, vision insurance, parental benefits including creche reimbursement, as well as a retirement plan, so that you can feel secure in your health, financial future and child care during work.
- Generous paid time off policy so that you can embrace a healthy work-life balance
- Fully catered lunch in our office along with a variety of healthy snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are excited to share more about our career opportunities with you through the interview process.