Logic Design Engineer
Description
Invent the future with us.
Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.
By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.
Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply!
About the role:
You will use your RTL design skills to implement complex SoCs for advanced ARMv8-based server systems and state-of-the-art communication components. You will collaborate closely with SoC architecture, DV (Design Verification), SE (Silicon Engineering) in active projects and sustaining engineering activities. Using your Verilog and System Verilog coding and problem-solving skills, you will design internally developed IPs as well as integrating 3rd party IPs. You will be responsible for the full life cycle of design, from specification creation and RTL coding to synthesis and timing closure.
What you’ll achieve:
- Create detailed design specifications based on architecture and micro-architecture specifications.
- Design RTL and coding for high-speed designs, optimized for high speed, low power, and area efficiency
- Develop RTL Linting and CDC scripts, evaluation of results, and corrective actions.
- Support silicon bring-up and silicon validation.
About you:
- Minimum 5+ years of SoC digital design experience
- Knowledge of SOC architecture, microarchitecture, logic and RTL design concepts
- Knowledge and/or experience with SoC AMBA bus architectures such as CHI, AXI, AHB, APB and advanced connectivity implementations such as Network-on-Chip (NoC)
- Knowledge or experience with HW coherence protocols, Fabric traffic management, including flow control, out-of-order queueing, arbitration and QoS, is a plus
- Strong in System Verilog RTL design, design for bandwidth and latency optimization
- Strong in scripting languages (PERL, Python, shell, etc.)
- RTL & gate simulation experience and good debugging skills
- Experience with Lint and CDC tools and flows
- Experience with synthesis and STA flows is a plus
- Good English communications skills and ability to communicate technical concepts clearly and work collaboratively in a team to get things done in a fast-paced environment.
- BS/ MS/ Ph.D in Electronic Engineering/ Computer Engineering or Equivalent.
What we’ll offer:
At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits. We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.
Benefits highlights include:
- Premium healthcare, personal accident, and fully paid social insurance scheme as well as annual health check, so that you can feel secure in your health and financial future.
- Generous paid time off policy so that you can embrace a healthy work-life balance.
- Daily catered lunch, a variety of snacks, energizing coffee or tea, and refreshing drinks to keep you fueled and focused throughout the day.
And there is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.