Senior Principal Engineer, Cache Coherency Subsystem Verification
Description
About the role:
As a Senior Principal Cache Coherency Subsystem Verification Engineer, you will the opportunity to work on and lead the verification of a server-class microprocessor-based Coherent Mesh interconnect subsystem. You'll be involved with all aspects of pre-silicon verification of the subsystem to ensure functional correctness and performance of our CPUs. You'll also partner with other teams to accelerate post-silicon validation and debugging of the product.
Design Verification is an integral part of the chip design process that ensures our customers get the absolute highest quality products that meets their functional and performance requirements. The DV Team at Ampere comprises of stellar folks who have dedicated themselves to the art and fun of design verification. We are a tightly-knit, fast-paced team who work extremely closely with our design and architecture partners to ensure no bug is left behind.
What you’ll achieve:
- Strategize and execute cache coherency subsystem verification efforts across verification platforms
- Review architecture and microarchitecture specs and influence design/microarchitecture decisions
- Define verification strategy and test plans for cache coherency subsystem verification
- Architect and lead development of verification collateral including test benches, random test generators and checkers
- Lead and contribute to day-to-day execution of all verification activities to meet tape out quality requirements
- Define post-si validation plans and debug post-silicon system level failures
- Mentor/guide the work of other engineers to achieve project goals
About you:
- Minimum MS & 8 years or BS & 12 years of IP and subsystem design verification experience
- Solid understanding of high-performance multi-core processor architecture and microarchitecture, especially OOO memory and cache coherency protocols
- Prior experience in verifying Arm AMBA (APB/AHB/AXI/ACE/CHI) protocols or other high performance interconnect protocols.
- Experienced in building new verification test benches using industry standard languages like System Verilog, UVM/OVM
- Programming experience in 1 or more languages common to the industry (e.g., C, C++)
- Experience in automating design/verification tasks using perl/python or other scripting languages
- Knowledge of ARM or x86 memory architecture and assembly language programming
- Prior experience in leading design verification efforts and strong verification mindset with excellent attention to detail
- Technical leadership skills like ability to articulate vision, inspire the team, plan, and organize team’s work, make difficult decisions
- Strong analytical and problem skills and able to communicate technical concepts, status, and issues clearly
- Previous experience in CPU/core design verification is preferred
- Previous experience in emulation, FPGA and post-silicon validation is preferred
- BS/MS Electrical Engineering or Computer Engineering
- Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401K retirement plan, so that you can feel secure in your health and financial future
- Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance
- A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the day
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